When an interrupt is generated within an electronic system, a data processor within the electronic system services the interrupt. That data processor accesses an appropriate interrupt register for information regarding that interrupt such that the data processor may perform appropriate operations in servicing that interrupt.
Referring to FIG. 1, an electronic system 100 is a multiprocessor electronic system and includes a first data processor 102, a second data processor 104, and a third data processor 106. The data processors 102, 104, and 106 service interrupts generated by any sources known to one of ordinary skill in the art of digital system design. Having a plurality of data processors 102, 104, and 106 speeds up the service of interrupts. The plurality of data processors 102, 104, and 106 may be comprised of any type of data processors as known to one of ordinary skill in the art of digital system design.
For example, the electronic system 100 may be part of a computer network peripheral device which interfaces a computer host system having the data processors 102, 104, and 106 to a network of computers. In that case, an interrupt is generated whenever a data packet has been received from the network of computers and needs to be processed by at least one of the plurality of data processors 102, 104, and 106. Alternatively, an interrupt is generated whenever a data packet has been sent from the computer host system to the network of computers.
In any case, when an interrupt is generated to the data processors 102, 104, and 106, one of those data processors 102, 104, and 106 services the interrupt. Servicing of the interrupt includes reading an appropriate interrupt register for information regarding the interrupt. The electronic system 100 includes a first interrupt register 112, a second interrupt register 114, and so on, up to an Nth interrupt register 116. The interrupt registers 112, 114, and 116 may be any type of data registers as known to one of ordinary skill in the art of digital system design.
When an interrupt is generated by an interrupt generating source, the address of a corresponding interrupt register is written to an address line 120. The corresponding interrupt register has information associated with that interrupt. An address decoder 122 decodes that address on the address line 120 such that information from the corresponding interrupt register is gated to a data bus 130. Thus, each output bit of an interrupt register is coupled to the data bus 130 via a tri-state buffer having an enable line coupled to an output line of the address decoder 122. The address decoder 122 selects the appropriate interrupt register having information associated with a particular interrupt. The address decoder 122 may be implemented in any way known to one of ordinary skill in the art of digital system design.
The plurality of data processors 102, 104, and 106 services an interrupt by reading the information from the data bus after the information is gated from the corresponding interrupt register for that interrupt onto the data bus 130. One of the data processors 102, 104, and 106 should service an interrupt. However, in a multiprocessor system, when an interrupt is generated, more than one data processor may attempt to service that interrupt with unpredictable results. Yet, including a system with a plurality of data processors is advantageous for faster service of interrupts.
Thus, a mechanism for synchronizing service of interrupts by a plurality of data processors in a multiprocessor system is desired.